FPGA port map note

Works:
COMPONENT_ACC:
acc PORT MAP
(
aclr => clr2acc,
clock => wr2acc,
data => ad_data,
result => result
);
COMPONENT_ad_fifo:
fifo PORT MAP
(
aclr => aclr,
result => result,
clock => clk,
rdreq => rdreq,
wrreq => wr2fifo,--wrreq,
q => q_fifo,--to ad_moudule interface
empty => fifo_empty,
full => fifo_full
);
============================================
Dos NOT work:
COMPONENT_ACC:
acc PORT MAP
(
aclr => clr2acc,
clock => wr2acc,
data => ad_data,
result(22 downto 7) => data
);
COMPONENT_ad_fifo:
fifo PORT MAP
(
aclr => aclr,
data => result(22 downto 7),
clock => clk,
rdreq => rdreq,
wrreq => wr2fifo,--wrreq,
q => q_fifo,--to ad_moudule interface
empty => fifo_empty,
full => fifo_full
);
============================================
Works:
result(22 downto 7) <= data;
COMPONENT_ACC:
acc PORT MAP
(
aclr => clr2acc,
clock => wr2acc,
data => ad_data,
result(22 downto 7) => data
);
COMPONENT_ad_fifo:
fifo PORT MAP
(
aclr => aclr,
data => result(22 downto 7),
clock => clk,
rdreq => rdreq,
wrreq => wr2fifo,--wrreq,
q => q_fifo,--to ad_moudule interface
empty => fifo_empty,
full => fifo_full
);
============================================
Signals with same name will be connected automatically.
Signals with differenet names should be connected explicitly.